In the semiconductor industry, Moore's law states that the number of transistors on a chip doubles approximately every two years. These exponential performance gains present a challenge to the semiconductor manufacturing industry, along with the dual challenges of promoting power savings and providing cooling efficiency. The industry addresses these challenges in multiple ways. Selecting the gate dielectric and gate electrode are critical choices in enabling device scaling, and compatibility with CMOS technology. Two main approaches have emerged in high-k and metal gate (HKMG) integration: gate-first and gate-last. Gate-last is also called replacement metal gate (RMG) where the gate electrode is deposited after S/D junctions are formed and the high-k gate dielectric is deposited at the beginning of the process (high-k first).
A high-k first gate-last process is when the high-k dielectric is deposited first and the metal is deposited last (gate-last method). Gate-last is often referred to as the replacement gate option. “First” and “last”-gate denotes whether the metal gate electrode is deposited before or after the high temperature anneal process. Typically, reliability of high-k gate stacks improve as a result of dopant activation anneal at temperatures around 1000° C., which is built in for gate-first or high-k first gate-last processes. The high-k last gate-last (replacement gate) process, however, lacks such built-in high temperature treatment, and thus reliability is a big challenge.
Referring now in specific detail to the drawings, and particularly to FIGS. 1A and 1B, there is provided a simplified pictorial illustration of the gate fabrication process using a hydrogen (H2) anneal, according to the known art. Hydrogen gas is favored for its gate oxide reliability. FIG. 1A shows H2 150 annealed directly on a high-k layer 110. The problems with this process are twofold: 1) the formation of oxygen vacancies in the high-k dielectric 110; and 2) an undesired Vt shift, causing gate leakage degradation.
In FIG. 1B we provide a simplified illustration of another gate fabrication process using an H2 anneal 150 on a full structure with a replacement gate 130 in place, according to the known art. In this method, the supply of hydrogen is blocked by the metal layers. Moreover, the degree of interface passivation depends on the device size (large devices can be un-passivated).
We provide a glossary of terms used throughout this disclosure:
Glossary
k—dielectric constant value
high-k—having a ‘k’ value higher than 3.9 k, the dielectric constant of silicon dioxide
CMOS—complementary metal-oxide semiconductor
FET—field effect transistor
FinFET—a fin-based, multigate FET
MOSFET—a metal-oxide semiconductor FET
CMP—chemical/mechanical polishing
Dit—interface states
RTA—rapid thermal anneal
HfO2—hafnium oxide
H2—hydrogen
D2—deuterium
A-Si—amorphous silicon
ALD—atomic layer deposition
PVD—physical vapor deposition
SiOx—silicon oxide
SiGe—silicon germanide
SiC—silicon carbide
RIE—reactive ion etching
ODL—optically dense layer; organically dielectric layer
STI—shallow trench isolation
S/D—source and drain terminals
NiSi—nickel silicide
C (DLC)—metal-free diamond-like carbon coating
SiN—silicon nitride
TDDB—time dependent dielectric breakdown
NBTI—negative bias temperature instability
PBTI—positive bias temperature instability
RTA—rapid thermal annealing
IL/HK—interfacial layer/high-k dielectric layer
TiN—titanium nitride
TiC—titanium carbide
TaN—tantalum nitride
TaC—tantalum carbide
TiAl—titanium aluminide
N2—nitrogen
Al—aluminide
W—tungsten
HfO2—Hafnium-based high-k dielectric